In recent years, technology of information confidentiality, in which, the data is encrypted and transmitted by a transmitter, and the data transmitted is received and decrypted by a receiver, so that the data is transmitted and received safely, has been known in the field of computer and communication. For example, in data communications using the network, in order to secure confidentiality and perfectibility of the data, the technique of encryption and message authentication are used. Further, the same technique is employed for protection and integrity securement of the files such as contents stored in the media.
Conventionally, for the execution of the encryption/decryption, message authentication, checksum and the like, a structure in which the execution performed mainly by software has been employed. This structure, which performs by software, can be used flexibly, however, as the predetermined processing becomes complicated, the processing time becomes longer, therefore, there is a problem that the processing throughput is deteriorated.
As one method to solve this problem, as disclosed in Japanese Patent Application Laid-Open Publication No. 2004-53716 (Patent Document 1) and Japanese Patent Application Laid-Open Publication No. 10-320191 (Patent Document 2), the method in which processing such as the encryption/decryption and the message authentication is performed by hardware processing circuit, so that the acceleration (speed-up) of the processing is achieved, is considered. That is, in this method, a data processing unit (accelerator) composed of hardware for speed-up corresponding to the specific processing such as encryption/decryption is provided. In this method, even if the specific processing is complicated, the deterioration of the processing throughput can be prevented.